1. Field
The present invention relates generally to compilers that compile high-level code to machine code and more specifically to the scheduling of instructions during compilation.
2. Background
In general, when a high-level language such as C or C++ is compiled to executable machine code a translation occurs from a human readable source code language (e.g., C or C++) into a processor executable machine language, which includes a set of machine instructions that are executable by a processor.
There are two widely used types of processor architectures: superscalar and very long instruction word (VLIW) architectures. The superscalar approach utilizes complex hardware that dynamically schedules around instruction dependencies at runtime to avoid certain hazards (e.g., x86, power PC, and ARM hardware). In the VLIW approach, much simpler hardware is utilized, which is generally incapable of dynamic conflict resolution. For this reason all instruction scheduling is done statically, during compile time. This allows for simpler hardware, but puts more of a burden on the compiler because the sequence of instructions that are produced by the compiler is the sequence that will be executed by the hardware. As a consequence, there is more of an emphasis on compile techniques in the VLIW approach.
Many manufacturers are opting for simpler hardware and shifting the complexity to compile time, but existing compilers are often either geared toward compiling for superscalar hardware or are otherwise unsatisfactory with respect to scheduling instructions for efficient execution. As a consequence, it would be desirable to improve compiler implementation to produce a more optimal sequence of instructions at compile time.